FPGA Projects

Think, Design & Build

Blocking vs Non-Blocking
Assign vs If statement
Basic gates using MUX
Half Adder
Full Adder
Ripple carry adder
Carry look ahead adder
Adder/Subtractor
Sign Magnitude Adder
Decoder using Combinational Logic
Decoder using Shift Operator
Encoder
Priority Encoder
Comparator
Binary to Gray code
Gray code to Binary
BCD to Excess 3
Excess 3 to BCD
D Flip Flop
Up Down Counter
Mod N Counter
Ring Counter
Johnson Counter
Ripple Counter
Dual Edge Binary Counter
Serial In Parallel Out (SIPO)
Parallel In Serial Out (PISO)
Universal Shift Register
Linear Feedback Shift Register (LFSR)
Random Access Memory (RAM)
Read Only Memory (ROM)
Multiplier using ROM (4-bit)
Arithmetic Unit (AE)
Logic Unit (AE)
Arithmetic Logic Unit (ALU)
Finite State Machine (FSM)
Timed FSM e.g. Traffic Lights
Clock Frequency Divider by an Odd Number
Clock Frequency Divider by an Even Number
UART Transmitter
UART Receiver
UART Project
Synchronous FIFO